1. Field of the Invention
The present invention relates generally to memory controllers in a computing system and more particularly to a memory controller in a computing system having an auxiliary buffer for write-once/read-once data.
2. Description of the Related Art
FIG. 1 shows a current computing system hardware platform 10 which employs an architecture in which a main bridge 12 (acting as a central switch) connects the processing element or elements 14, peripheral device adapters (including an auxiliary bridge) 16-18 and graphics subsystem 20 to the main memory 22, which is the primary repository for data and instructions for the processing element 14, the peripherals 16-18 and the graphics subsystem 20. A local memory 24 for storing graphics data is typically connected to the graphics subsystem 20. The main bridge 12 handles a large amount of data traffic because virtually all of the data, which the processing element 14, the peripherals 16-18 and the graphics subsystem 20 need, must move through the main bridge 12 to and from the main memory 22. In particular, not only does the main bridge 12 allow the processing element(s) 14, the peripheral adapters 16-18 and the graphics interface to access main memory, but it also permits the processing element(s) 14, and the bus adapters 16-18 to access the local graphics memory 24.
A hardware platform embodying the architecture of FIG. 1 has been adequate for much of the computing that takes place on such a platform. However, the processing element, peripherals and graphics subsystem have each been improved. Faster processing elements now demand gigabytes per second from the main memory; peripheral systems transfer data at speeds of hundreds of megabytes per second; and graphics subsystems are capable of rendering more than 50 Million polygons (triangles) per second. The combined load, which might be as high as 3.0 Gigabytes per second, must be borne by the main memory system and the bus that connects that system to the main bridge. As might be expected, the main memory and main memory bus have proved to be a barrier to further increases in system performance for the above architecture.
As mentioned above, the graphics subsystem has played a significant role in the increasing traffic load to and from the main memory. In particular, if a graphics subsystem intends to render 50 Million triangles per second, wherein each new triangle is defined by a single vertex of 30 bytes, the load on the memory is approximately 1500 Megabytes per second to store the data in memory and 1500 Megabytes per second to retrieve the data from memory, for a total of 3 Gigabytes per second, just for the graphics system.
Even if the memory system has a wide bus, say 16 bytes, the memory system must produce at least 187.5 Million cycles per second to handle a data transfer of about 3 Gigabytes in one second. Currently, main memory systems designed for this type of platform cannot deliver this data transfer requirement and, as a result, each device that is connected to the main bridge suffers a larger latency and lower overall transfer rate.
Thus, there is a need to improve the performance of such systems having a main bridge without radically altering the architecture that is already in place for these systems. The need is particularly acute with respect to the graphics subsystems which will need even more bandwidth to handle 3D graphics applications.
The present invention meets the above need. A method of accessing a memory with an auxiliary buffer, in accordance with the present invention, includes the following steps. First, a memory request having an address specifying a location in memory is received. The memory request has a type which is either xe2x80x98readxe2x80x99 or xe2x80x98writexe2x80x99, and the write request includes write data. Next, the address of the memory request is tested to determine whether it is within a predetermined range of addresses in the memory. If the request is in-range and if the request is a write request and the address in the write request matches the write pointer, then the buffer is written with the write data at the location specified in the write pointer and the write pointer is altered after writing the buffer to point to the next location for writing in the buffer. If the request is in range and the request is a read request and the address in the read request matches the read pointer, the buffer is read from the location specified in the read pointer and the read pointer is altered after reading the buffer to point to the next location for reading the buffer.
A buffering system for a memory that receives memory requests, the memory request having an address specifying a location in memory and a type being either a read or a write, a write request including write data, in accordance with the present invention, includes a decoder for determining whether the memory request is within a predetermined range of addresses in the memory based on the address of the request and generating an in-range indicator.
Further included is comparison circuitry for indicating when the address in the request matches either the read pointer or write pointer in response to the in-range indicator, for indicating when the address and the read pointer are equal, and for indicating when the address of a request is between the write pointer and read pointer.
An auxiliary buffer controller is included for performing read and write operations on the auxiliary buffer. The auxiliary buffer controller includes means for writing the buffer with the write data at the location specified in the write pointer and for reading the buffer from the location specified in the read pointer in response to a write-pointer match or a read pointer match, and means for making available some or all of the contents of the auxiliary buffer for writing to the memory in response to an indication that the address of a request is between the write pointer and read pointer, and in response to an indication that the address equals the read pointer after a buffer write operation.
Also included in the buffering system is pointer circuitry for updating the write pointer after writing the buffer to point to the next location for writing in the buffer in response to a write-pointer match, and for updating the read pointer after reading the buffer to point to the next location for reading the buffer in response to a read-pointer match.
Finally, an auxiliary buffer is included. The auxiliary buffer is connected to the memory and to auxiliary buffer controller means, for holding write-once, read-once data.
One advantage of the present invention is that data that is ordinarily written once to memory only to be read once thereafter need never be stored in main memory. This prevents the data from tying up the main memory bus twice, once when written and once when read, thereby freeing up the main memory bus for other memory data that is more useful to store in main memory.
Another advantage of the present invention is that peripheral subsystems, utilizing write-once, read-once data, are not required to change because the addition of the auxiliary buffer does not affect the operation of those subsystems, except to provide lower latency access to the data.
Yet another advantage of the present invention is that other parts of the computing platform are sped up because some or all of the write-once, read-once traffic is removed from the memory bus. This enables other peripherals to have access to the main memory when they would otherwise wait.
Yet another advantage is lower power consumption in the system because the external memory interface, whose I/O interface consumes appreciable power, and the internal circuitry of the memory devices connected to the external memory interface, are less active.